1. Field of the Invention
The present invention relates to a system for interconnecting a multiple die assembly to a printed circuit board or other substrate.
2. Description of Related Art
FIG. 1 is a simplified sectional elevation view of a prior art multiple die electrical system 10 including a multiple die assembly 12 mounted on a printed circuit board (PCB) or other substrate 14. Multiple die assembly 12 includes a set of secondary dice 16-18 mounted directly on a base die 20 within an integrated circuit (IC) package 28. Solder 22 conductively links bond pads 24 on dice 16-18 to bond pads 26 on die 20. An IC socket 36 mounted on substrate 14 releasably secures and interconnects each package pin 34 through a contact 37 and a solder ball 38 to one of a set of traces 39 on PCB 14. Bond wires 30 link various bond pads 32 on base die 20 to package pins 34. For illustration purposes solder 22 is shown much thicker than it would be after being melted and re-solidified to bond pads 24 to pads 26. While only two package pins 34 are shown in FIG. 1, a typical IC package will have many package pins.
Multiple die assemblies including one or more secondary dice directly mounted on a base die are often used where high frequency communication between die is needed because the relatively short signal paths between the secondary and base dice can convey high frequency signals. For example multiple die assemblies have been used to link dice implementing random access memories (RAMs) to a die implementing a microprocessor so the microprocessor can read and write access the RAMS at their highest rates without being limited by the bandwidth of the interconnection.
FIG. 2 is a simplified block diagram of a prior art computer system 40 including a processor die 42, a random access memory (RAM) die 44 and a read only memory (ROM) die 46. Processor die 42 contains a processor 48, a bus interface circuit 50 and an internal bus 52 connecting processor 48 to bus interface circuit 50. Bus interface circuit 50 links processor 48 to RAM die 44 and ROM die 46 through a parallel memory bus 54 and to other IC devices 56 through a parallel input/output (I/O) bus 58. The speed with which processor 48 communicates with RAM die 44, ROM die 46 and other devices 56 is a function of the frequency of signals conveyed by buses 54 and 58; the higher the signal frequency, the faster the communication. However shunt capacitances and series inductances of buses 54 and 58 attenuate and distort signals; the higher the signal frequency the greater the signal attenuation and distortion. Hence we must limit frequencies of signals on buses 54 and 58 to levels for which signal attenuation and distortion remain within acceptable limits.
Since the shunt capacitance and series inductance of a bus are increasing functions of bus length, we can increase bus operating frequency limits by reducing the length of the bus. To reduce signal path distances of bus 54 the dice 44 and 46 implementing RAM and ROM could be mounted directly on processor die 42. Thus, for example, one or more of secondary die 16-18 of FIG. 1 could implement RAM and ROM and base die 20 could implement a processor die.
It is possible to test multiple die assembly 12 of FIG. 1 before packaging it using test equipment accessing pads 32 through test probes. However since the probes may not have the same impedance characteristics as bond wires 30 and package pins 34, the test interconnect environment may not accurately model the operating interconnect environment of assembly 12 when later installed in package 28 and interconnected with PCB 14 through bond wires 30 and package pins 34. Thus the test may overestimate or underestimate the effects of signal attenuation and distortion caused by bond wires 30 and package pins 34.
While the multiple die assembly architecture of FIG. 1 can link RAM and ROM dice 44 and 46 to processor die 42 through short signal paths, processor die 42 must still communicate with other I/O devices 56 that may be mounted on PCB substrate 14 of FIG. 3 through relatively long signal paths formed by bond wires 30, package pins 34 and socket 36. One way to reduce signal path lengths between the base die 20 and the PCB substrate 14 has been to mount the base die directly on the substrate and link the circuits on the upper surface of the base die to the substrate through vias passing vertically through the base die.
FIG. 3 is a simplified sectional elevation view of a prior art multiple die assembly 60 including secondary die 62-64 mounted on and linked to a base die 66 generally similar to multiple die assembly 12 of FIG. 1. However while the system of FIG. 1 packages the multiple die assembly 12 and uses bond wires 30, package pins 34 and connector 37 to link pads 32 on base die 20 to traces 39 on PCB substrate 14, the system of FIG. 3 mounts base die 66 directly on a PCB substrate 68 and uses conductive vias 70 passing though base die 66 and solder 72 to link pads 74 on an upper surface of the base die to traces 76 on substrate 68. Vias 70 provide shorter signal pathways than the bond wires 30 and package pins 34 of system 10 (FIG. 1). However vias 70 are difficult and expensive to fabricate.
Thus what is needed is a system that can reduce signal path lengths between a base die of a multi-die assembly and a PCB or other substrate without having to form vias through the base die. The system should also permit IC testers to access the base and secondary dice through signal paths having similar impedance characteristics to the paths later used to interconnect them to one another and to a PCB or other substrate.